This invention relates to semiconductor devices and more particularly to semiconductor devices utilizing redundancy techniques.
Recently, semiconductor devices, particularly semiconductor memory devices, comprise a spare device in addition to a normal device. Semiconductor devices utilizing such redundancy techniques have been used with greater frequency. A semiconductor memory which utilizes a redundancy technique comprises spare memory cells in addition to normal memory cells. When a defective bit is detected in one of the normal memory cells after fabrication, the defective memory cell is replaced by a spare memory cell. A semiconductor memory device, even if only one bit is defective, is generally regarded as a substandard device. As the capacity of memory devices increases, defective memory cells tend to occur at a greater frequency. If a memory device in discarded, even though only one bit is found to be defective, the semiconductor memory device would be manufactured with a low yield and at a high cost. It is for this reason that the redundancy technique has been accepted.
To effect replacement of a defective normal memory cell by a spare memory cell data are programmed in a nonvolatile memory element by a programming element. This memory element is commonly prepared from a polysilicone fuse.
FIG. 1A indicates the arrangement of a conventional programming element. A polysilicon fuse 10 is connected between a power supply terminal VDD and an output terminal OUT. Connected in parallel between the output terminal OUT and ground are an enhancement mode MOSFET 12 for programming (unless noted otherwise, the MOSFET is chosen to be an N-channel type) and a depletion mode MOSFET 14. A programming signal P is supplied to the gate of the MOSFET 12, and the gate of the MOSFET 14 is grounded.
With the above-mentioned conventional programming element, binary data is programmed by the blown or connected condition of the polysilicon fuse 10. When, at the time of programming, a programming signal P has a logic level "1", then the MOSFET 12 is rendered conductive, causing current to flow through the fuse 10. At this time, the fuse 10 is blown by the released Joul heat. When the fuse 10 is blown, the output terminal OUT is set at a logic level "0" through the MOSFET 14. Conversely, when a programming signal P has a logic level "0" at the time of programming, then the MOSFET 12 is rendered nonconductive preventing the fuse 10 from being blown. At this time, the output terminal OUT is set at a logic level "1" by the ratio between the resistances of the fuse 10 and MOSFET 14.
FIG. 1B indicates the arrangement of another conventional programming element which produces an output signal having a different level from FIG. 1A. In FIG. 1B, when the fuse 10 is blown, an output signal has a logic level "1". When the fuse 10 is connected, an output signal has a logic level "0".
With the above-mentioned conventional programming element, when the fuse 10 is not blown, current always flows through the fuse 10. The fuse 10 can be blown not only by the passage of current but also by the impingement of laser beams. The fuse 10 is generally made narrow so as to be easily blown. From the standpoint of prescribing the reliability of a programming element, therefore, it is not desirable to let current always run through the fuse. For example, when the power source voltage jumps for some reason, and a large current flows through the fuse 10, the fuse tends to blow.